Preface i x1 Digital Systems and Binary Numbers 11.1 Digital Systems 11.2 Binary Numbers 31.3 Number-Base Conversions 61.4 Octal and Hexadecimal Numbers 81.5 Complements of Numbers 101.6 Signed Binary Numbers 141.7 Binary Codes 181.8 Binary Storage and Registers 271.9 Binary Logic 302 Boolean Algebra and Logic Gates 382.1 Introduction 382.2 Basic Definitions 382.3 Axiomatic Definition of Boolean Algebra 402.4 Basic Theorems and Properties of Boolean Algebra 432.5 Boolean Functions 462.6 Canonical and Standard Forms 512.7 Other Logic Operations 582.8 Digital Logic Gates 602.9 Integrated Circuits 663 Gate-Level Minimization 733.1 Introduction 733.2 The Map Method 733.3 Four-Variable K-Map 803.4 Product-of-Sums Simplification 843.5 Don't-Care Conditions 883.6 NAND and NOR Implementation 903.7 Other Two-Level Implementations 973.8 Exclusive-OR Function 1033.9 Hardware Description Language 1084 Combinational Logic 1254.1 Introduction 1254.2 Combinational Circuits 1254.3 Analysis Procedure 1264.4 Design Procedure 1294.5 Binary Adder-Subtractor 1334.6 Decimal Adder 1444.7 Binary Multiplier 1464.8 Magnitude Comparator 1484.9 Decoders 1504.10 Encoders 1554.11 Multiplexers 1584.12 HDL Models of Combinational Circuits 1645 Synchronous Sequential Logic 1905.1 Introduction 1905.2 Sequential Circuits 1905.3 Storage Elements: Latches 1935.4 Storage Elements: Flip-Flops 1965.5 Analysis of Clocked Sequential Circuits 2045.6 Synthesizable HDL Models of Sequential Circuits 2175.7 State Reduction and Assignment 2315.8 Design Procedure 2366 Registers and Counters 2556.1 Registers 2556.2 Shift Registers 2586.3 Ripple Counters 2666.4 Synchronous Counters 2716.5 Other Counters 2786.6 HDL for Registers and Counters 2837 Memory and Programmable Logic 2997.1 Introduction 2997.2 Random-Access Memory 3007.3 Memory Decoding 3077.4 Error Detection and Correction 3127.5 Read-Only Memory 3157.6 Programmable Logic Array 3217.7 Programmable Array Logic 3257.8 Sequential Programmable Devices 3298 Design at the Register Transfer Level 3518.1 Introduction 3518.2 Register Transfer Level Notation 3518.3 Register Transfer Level in HDL 3548.4 Algorithmic State Machines (ASMs) 3638.5 Design Example (ASMD CHART) 3718.6 HDL Description of Design Example 3818.7 Sequential Binary Multiplier 3918.8 Control Logic 3968.9 HDL Description of Binary Multiplier 4028.10 Design with Multiplexers 4118.11 Race-Free Design (Software Race Conditions) 4228.12 Latch-Free Design (Why Waste Silicon?) 4258.13 Other Language Features 4269 Laboratory Experiments with Standard ICs and FPGAs 4389.1 Introduction to Experiments 4389.2 Experiment 1: Binary and Decimal Numbers 4439.3 Experiment 2: Digital Logic Gates 4469.4 Experiment 3: Simplification of Boolean Functions 4489.5 Experiment 4: Combinational Circuits 4509.6 Experiment 5: Code Converters 4529.7 Experiment 6: Design with Multiplexers 4539.8 Experiment 7: Adders and Subtractors 4559.9 Experiment 8: Flip-Flops 4579.10 Experiment 9: Sequential Circuits 4609.11 Experiment 10: Counters 4619.12 Experiment 11: Shift Registers 4639.13 Experiment 12: Serial Addition 4669.14 Experiment 13: Memory Unit 4679.15 Experiment 14: Lamp Handball 4699.17 Experiment 16: Parallel Adder and Accumulator 4759.18 Experiment 17: Binary Multiplier 4789.19 Verilog HDL Simulation Experiments and Rapid Prototyping with FPGAs 48010 Standard Graphic Symbols 48810.1 Rectangular-Shape Symbols 48810.2 Qualifying Symbols 49110.3 Dependency Notation 49310.4 Symbols for Combinational Elements 49510.5 Symbols for Flip-Flops 49710.6 Symbols for Registers 49910.7 Symbols for Counters 50210.8 Symbol for RAM 504Appendix 507Answers to Selected Problems 521Index 539