The Verilog Programming Language Interface, commonly called the
Verilog PU, is one of the more powerful features of Verilog. The PU
provides a means for both hardware designers and software engineers to
interface their own programs to commercial Verilog simulators. Through
this interface, a Verilog simulator can be customized to perform
virtually any engineering task desired. Just a few of the common uses
of the PU include interfacing Veri log simulations to C language
models, adding custom graphical tools to a simulator, reading and
writing proprietary file formats from within a simulation, performing
test coverage analysis during simulation, and so forth. The
applications possible with the Verilog PLI are endless. Intended
audience: this book is written for digital design engineers with a
background in the Verilog Hardware Description Language and a
fundamental knowledge of the C programming language. It is expected
that thereader: Has a basic knowledge of hardware engineering,
specifically digital design of ASIC and FPGA technologies. Is familiar
with the Verilog Hardware Description Language (HDL), and can write
models of hardware circuits in Verilog, can write simulation test
fixtures in Verilog, and can run at least one Verilog logic simulator.
Knows basic C-language programming, including the use of functions,
pointers, structures and file I/O. Explanations of the concepts and
terminology of digital
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Produktdetaljer
ISBN
9781461550174
Publisert
2020
Utgiver
Vendor
Springer
Språk
Product language
Engelsk
Format
Product format
Digital bok
Forfatter