Preface 1 Digital Design Using VHDL and PLDs 1 1.1 VHDL/PLD Design Methodology 1 1.2 Requirements Analysis and Specification 5 1.3 VHDL Design Description 6 1.4 Verification Using Simulation 11 1.5 Testbenches 13 1.6 Functional (Behavioral) Simulation 16 1.7 Programmable Logic Devices (PLDs) 18 1.8 SPLDs and the 22V10 21 1.9 Logic Synthesis for the Target PLD 27 1.10 Place-and-Route and Timing Simulation 31 1.11 Programming and Verifying a Target PLD 37 1.12 VHDL/PLD Design Methodology Advantages 38 1.13 VHDL’s Development 39 1.14 VHDL for Synthesis versus VHDL for Simulation 39 1.15 This Book’s Primary Objective 40   2 Entities , Architectures , and Coding Styles 44 2.1 Design Units, Library Units, and Design Entities 44 2.2 Entity Declaration 45 2.3 VHDL Syntax Definitions 47 2.4 Port Modes 50 2.5 Architecture Body 53 2.6 Coding Styles 55 2.7 Synthesis Results versus Coding Style 66 2.8 Levels of Abstraction and Synthesis 69 2.9 Design Hierarchy and Structural Style 71   3 Signals and Data Types 823.1 Object Classes and Object Types 82 3.2 Signal Objects 84 3.3 Scalar Types 88 3.4 Type Std_Logic 93 3.5 Scalar Literals and Scalar Constants 99 3.6 Composite Types 100 3.7 Arrays 101 3.8 Types Unsigned and Signed 107 3.9 Composite Literals and Composite Constants 110 3.10 Integer Types 112 3.11 Port Types for Synthesis 116 3.12 Operators and Expressions 118   4 Dataf low Style Combinational Design 1234.1 Logical Operators 123 4.2 Signal Assignments in Dataflow Style Architectures 127 4.3 Selected Signal Assignment 130 4.4 Type Boolean and the Relational Operators 132 4.5 Conditional Signal Assignment 134 4.6 Priority Encoders 139 4.7 Don’t Care Inputs and Outputs 140 4.8 Decoders 144 4.9 Table Lookup 147 4.10 Three-state Buffers 151 4.11 Avoiding Combinational Loops 155   5 Behavi oral Style Combinational Design 165 5.1 Behavioral Style Architecture 165 5.2 Process Statement 169 5.3 Sequential Statements 170 5.4 Case Statement 171 5.5 If Statement 176 5.6 Loop Statement 181 5.7 Variables 185 5.8 Parity Detector Example 188 5.9 Synthesis of Processes Describing Combinational Systems 193   6 Event-Driven Simulation 2016.1 Simulator Approaches 201 6.2 Elaboration 203 6.3

Logical Progression - Readers can begin producing synthesizable designs quickly because mastery of the VHDL language and usage progresses in step-wise fashion from simple to complex.Streamlined Coverage - VHDL constructs that are not useful for writing synthesizable design descriptions or testbenches are not covered in the text.Focus on Methodology - Design methodology and examples presented in the book are independent of any particular set of VHDL software tools or target PDL devices, to ensure that concepts are the focus. As a nonproprietary standard, VHDL designs are portable to other vendors' software tools and/or PLDs.Design Flow - Focus on the design flow in the VHDL/PLD design methodology is used in each step.Applied Learning - More then 275 block diagrams, logic diagrams, and timing waveforms and 180+ program listings illustrate the design concepts, cementing the VHDL/PLD design methodology.Professional Standards - Programming examples are compliant with the IEEE standard 1076-2002 for simulation and the IEEE standard 1076.6-2004 for synthesis.Student Software - Aldec Active-HDLTM 7.2 Student Edition Software, an ideal design and simulation environment for learning VHDL, is packaged with each text.This text also establishes a useful starting point for VHDL- based application-specific integrated circuits (ASICs) design. Similar processes are used to synthesize and test PLDs and to synthesize and test ASICs.