This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students, and professionals engaged in the domain of FPGA circuit optimization and implementation.

Describes the optimized implementations of several arithmetic data path, control path and pseudorandom sequence generator circuits Proposed designs outperform and have superior operand-width scalability, compared to implementations based on native DSP hard macros provided by Xilinx or those derived by the traditional Behavioral HDL-to-implementation design flow Proposes a unified framework to design and implement high performance integer arithmetic circuits using "fabric logic" available on the leading FPGA platforms from Xilinx Provides detailed mathematical analysis aimed at deriving the proposed architectures step-by-step Describes and implements Design automation of the proposed design methodology, which integrates easily into the standard (non-licensed) Xilinx ISE design environment Includes supplementary material: sn.pub/extras