This text discusses the introduction of innovative power estimation and optimization methodologies to support the design of low power embedded systems based on high-performance Very Long Instruction Word (VLIW) microprocessors. A VLIW processor is a (generally) pipelined processor that can execute, in each clock cycle, a set of explicitly parallel operations; this set of operations is statically scheduled to form a Very Long Instruction Word. The proposed estimation techniques are integrated into a set of tools operating at the instruction level and they are characterized by efficiency and accuracy. The aim is the definition of an overall power estimation framework, from a system-level perspective, where novel power optimization techniques can be evaluated. The proposed power optimization techniques are addressed to the micro-architectural as well as the system level. Two main optimization techniques have been proposed: the definition of register file write inhibition schemes that exploit the forwarding paths, and the definition of a design exploration framework for an efficient fine-tuning of the configurable modules of an embedded system.