Welcome to the world of Verilog! I have been using Verilog since 1986 and teaching Verilog since 1987. I have seen many different Verilog courses and many approaches to learning Verilog. If you want a Verilog reference, I suggest one of the Open Verilog International (OVI) reference manuals.

1 Introduction.- Framing Verilog Concepts.- Where To Get More Information.- 2 Introduction to the Verilog Language.- Identifiers.- White Space.- Comments.- Numbers.- Text Macros.- Modules.- Semicolons.- Value Set.- Strengths.- Numbers, Values, and Unknowns.- 3 Structural Modeling.- Primitives.- Ports.- Instances.- Hierarchy.- Hierarchical Names.- 4 Behavioral Modeling.- Starting Places for Places for Blocks of Behavioral Code.- System Tasks for Printing Out Results.- Data Objects in Verilog.- Procedural Assignments.- Ports and Registers.- 5 Operators.- Binary Operators.- Unary Operators.- Reduction Operators.- Ternary Operator.- Equality Operators.- Concatenations.- Logical versus Bit-wise Operations.- Operations That Are Not Legal on Reals.- Working with Strings.- Combining Operators.- Sizing Expressions.- 6 Working with Behavioral Modeling.- Continuous Assignment.- Event Control.- The if Statement.- The case Statement.- Loops.- Procedural Continuous Assignments.- tasks.- functions.- A Reminder about Ports and Registers.- Modeling with inout Ports.- Named Blocks.- The disable Statement.- When is a Simulation Done.- 7 User-Defined Primitives.- Combinatorial UDPs.- Sequential UDPs.- UDP Instances.- The Final Details.- 8 Parameterized Modules.- n-Bit Mux.- n-Bit Adder.- n By m Mux.- n By m Ram.- Using Parameterized Modules.- 9 State Machines.- State Machine Types.- State Machine Modeling Style.- State Encoding Methods.- Default Conditions.- Implicit State Machines.- Registered and Unregistered Outputs.- Factors in Choosing a State Machine Modeling Style.- 10 Modeling Tips.- Modeling Combinatorial Logic.- Modeling Sequential Logic.- Modeling Asynchronous Circuits.- Special-Purpose Models.- Multiplier Examples.- A Proven, Successful Approach to Modeling.- 11 Modeling StyleTrade-Offs.- Forces That Influence Modeling Style.- Learning From Other People’ s Mistakes.- When To Use UDPs.- 12 Test Benches and Test Management.- to Testing.- Response-Driven Stimulus.- Test Benches for Inouts.- Loading Files into Verilog Memories.- Test Benches with No Test Vectors.- Using a Script To Run Test Cases.- Modeling BIST.- The Surround and Capture Method.- 13 Common Errors.- Mismatched Ports.- Missing or Incorrect Declarations.- Improper Use of Procedural Continuous Assignments.- Missing initial or always Blocks.- Zero-Delay always Loops.- initial Instead of always.- Missing Initialization.- Overly Complex Code.- Unintended Storage.- Timing Errors.- 14 Debugging A Design.- Overview of Functional Debugging.- Universal Techniques.- Using Waveforms.- Interactive Debugging.- Catching Problems Later in a Simulation.- Isolating Differences in Models.- Summary of Debugging.- Appendix A Gate Level Details.- Primitive Descriptions.- Logic Gates.- AND.- NAND.- OR.- NOR.- XOR.- XNOR.- Buffers.- BUF.- NOT.- BUFIFO.- BUHF1.- NOTIF0.- NOTIF1.- PULLDOWN.- PULLUP.- Switches.- NMOS and RNMOS.- PMOS and RPMOS.- CMOS and RCMOS.- TRAN and RTRAN.- TRANIFO and RTRANIFO.- TRANIF1 and RTRANIF1.- Instance Details.- Delays.- Delay Units.- Printing Out Time and the Timescale.- Strengths.- Strength reduction of switch primitives.- Appendix B Example Summary.

GPSR Compliance The European Union's (EU) General Product Safety Regulation (GPSR) is a set of rules that requires consumer products to be safe and our obligations to ensure this. If you have any concerns about our products you can contact us on ProductSafety@springernature.com. In case Publisher is established outside the EU, the EU authorized representative is: Springer Nature Customer Service Center GmbH Europaplatz 3 69115 Heidelberg, Germany ProductSafety@springernature.com